VLSI System and Computation Lab

WE ENGINEER EXCELLENCE

Symbolic Modeling and Analysis of Analog/Mixed-Signal Circuits

August 01, 2005

Principle Investigator

 

Graduate Students

  • Xue-Xin Liu,
  • Zhigang Hao

 

Collaborators

  • Prof. Esteban Tlelo-Cuautle, Institute National Astrophysics, Optical and Electrics (INAOE) of Mexico
  • Prof. Guoyong Shi, Institute of Microelectronics, Shanghai Jiaotong University.

 

Funding supports

We appreciate the following funding agencies for their generous supports of this project.

  • National Science Foundation, “CAREER: Career Development Plan: Behavioral Modeling, Simulation and Optimization for Mixed-Signal System in a Chip”, (CCF-0448534, CCF-0529754 and CCF-0731962, CCF- 0830304, for REU supplements), 6/1/2005-5/31/2011. PI: Sheldon Tan.
  • UC Micro Program (via Cadence Design Systems Inc.), #06-252, “Behavioral and compact modeling of mixed-signal and RF circuits”, , 7/1/2006-6/30/2007, PI: Sheldon Tan
  • National Science Foundation, “SHF:Small:Variational and Bound Performance Analysis of Nanometer Mixed-Signal/Analog Circuits”, CCF-1116882, 8/1/2011 to 7/31/2014, PI: Sheldon Tan
  • UC-MEXUS-CONACYT, “Symbolic modeling and reduction for analog/RF circuits and on-chip interconnect”, 8/1/2009 to 1/31/2011, PI: Sheldon Tan, co-PI: Esteban Tlelo-Cuaulte.
  • UC-MEXUS-CONACYT, “Symbolic and Statistical Modeling and Analysis Techniques for Analog/Mixed-Signal Nanometer Integrated Circuits”, 8/1/2011 to 2/31/2013, PI: Sheldon Tan, co-PI: Esteban Tlelo-Cuaulte.

 

Project Descriptions

Symbolic analysis is a systematic approach to obtaining the knowledge of analog building blocks in an analytic form. It is an essential complement to numerical simulation. Research on symbolic analysis can be dated back to 19th century. Developments in this field gained real momentum in the 1950’s when electric computers were introduced and used in circuit analysis. The first general-purpose circuit analysis programs emerged until early 1960s, where the basic concepts behind computer-aided design and analysis of analog circuits were to formulate network equations by matrix algebraic topological techniques. The major works during that time were based on six formulation schemes: nodal, state variable, hybrid, tableau, signal flow, and ports. Among them, the nodal analysis method was adopted for the development of SPICE, which has been proven to be very popular from early 1970s.

Various methods are proposed to solve the long-standing circuit-size problem. For instance, several methods have been accompanied with the development of three kinds of procedures to reduce or simplify the final symbolic expression, they are: simplification before the generation (SBG), simplification during generation (SDG), and simplification after generation (SAG). Besides, symbolic model order reduction techniques become to be another kind of simplification very useful for VLSI circuits. Furthermore, the strategies used in modern symbolic analyzers in general come in two categories: those based on hierarchical decompositions, and those based on approximations.

The PI (along with Prof. Richard Shi of U of Washington) proposed a graph-based symbolic analysis technique in 1997 [C1,B2,J1], which turns out to be a breakthrough method as the new method can significantly increase the capacity of symbolic analysis (from analog circuits with a few nodes to circuits with 20-30 nodes such as complex circuit like ua741 for the first time). At the heart of this approach is the introduction of Determinant Decisions Diagrams to represent determinant symbolically. As indicated by [D1, J1], the typical size of DDD is dramatically smaller than that of product terms. For instance, 5.71× 1020 terms can be represented by a diagram with 398 vertices. Further, similar to the expanded form, our representation is canonical, i.e., every determinant has a unique representation, and is amenable to symbolic manipulations. DDD is shown in the following figure and it represents the determinant in the (1).

 

det(M)  = adgj - adhi - aefj - bcgj + cbih  (1)


The power of DDD not only lies in the compactness for representing the terms in a determinant, but also the capability to manipulating the symbolic terms. Once DDDs are constructed, s-expanded symbolic polynomials and the dominate terms can be found by finding the shortest paths[J4,C4], which leads to efficient way to derive the interpretable symbolic expressions for gaining better insights and behavioral modeling. Compact model order reduction can also be preformed by symbolic hierarchical analysis and reduction [J2,J6,C8]. The hierarchical approaches essentially allow the symbolic analysis of analog circuits to be arbitrary large [J2,J7,C11]. The PI also proposed a very efficient way to construct DDDs graph based a logic circuit synthesis and bindery decision diagrams (BDD) [J8, C12]. The proposed DDD symbolic analysis techniques have been implemented in the software package called, SCAD3 (Symbolic Circuit Analysis with Determinant Decision Diagrams – SCAD3) [D1], which can be obtained upon request (See the software download below).


Recently Prof. Guoyiong Shi of SJTU approved that in the best case, DDD representation for the dense matrix still has exponential growth and provide a vertex ordering for this case. But compared to the original term growth rate of a determinant of a dense matrix, the DDD grow the rate is much smaller (Shi, TCAS-II, 2010).

Dr. G. Shi’s group also proposed a new graph-based approach based on spanning-trees instead of matrix expansion, which seems more amenable for sensitivity analysis than DDD graphs.

Dr. Esteban Tlelo-Cuautle of INAOE also made a number of contributions for symbolic analysis for analog circuits and power circuits using nullers[J9, C13,C14,C15], which are powerful modeling tools to deal with current and voltage mirrors in analog/mixed-signal circuits.

DDD based techniques recently has been extended to perform fast Monte-Carlo analysis based on GPU platform [B7,C16] and bound variational analog analysis [C17], which are the new emerging applications for DDD based symbolic analysis.

 

Invited Presentations

  • University of California at San Diego, Department of Electrical and Computer Engineering, San Diego, CA, “Symbolic Analysis of Analog Circuits with Determinant Decision Diagrams”, Feb. 4, 2003.
  • Fujitsu American Research Lab, Sunnyvale, CA, “Modeling and Simulation for Mixed-Signal System-On-a-Chip Designs”, Aug. 21, 2003.
  • Synposys Corporation Inc., San Jose, CA, “A General MIMO Linear Network Reduction and Realization”, Oct. 11, 2004.
  • Qualcomm, San Diego, CA, “Modeling and simulation research at MSLAB at UCR”, Feb. 13, 2008.
  • International Workshop on Emerging Circuits and Systems (IWECS’11), Hangzhou, Zhejiang Provence, China, “”Graph-based Parallel and Statistical Analysis of Large Analog Circuits Based on GPU Platforms, August 4, 2011.
  • The University of Hong Kong, Department of Electrical and Electronic Engineering, Hong Kong, China, “Graph-based Parallel and Statistical Analysis of Analog Circuits Based on GPU Platforms”, Hong Kong, Aug. 23, 2011.
  • The EDA workshop, Department of Electrical Engineering, National Taiwan University, Taiwan, “Performance Bound Analysis for Analog Circuits Under Process Variations”, Sept 10, 2011.

 

Software package releases

The DDD symbolic analysis tool suite, SCAD3 (with source codes and examples) can be obtained from Github at here

Relevant Publications

Books and chapters and PhD thesis

  • Guoyong Shi, Sheldon X.-D. Tan, Esteban Tlelo-Cuautle, “Advanced Symbolic Analysis for VLSI Systems -- Methods and Applications”, Springer Publisher, 2014, ISBN 978-1-4939-1103-5
  • Zhanhai Qin, Sheldon X.-D. Tan and Chung-Kuan Cheng, Symbolic Analysis and Reduction of VLSI Circuits, Springer Publisher, 2005, ISBN: 0-387-23904-9; e-ISBN: 0-387-23905-7.
  • C.-J. Shi and X.-D. Tan, “Canonical Symbolic Analysis of Large Analog Circuits with Determinant Decision Diagrams” Part III and pp.344-361 in Computer-Aided Design of Analog Integrated Circuit and Systems, R. A. Rutenbar, G. E. Gielen and B. A. Antao (ed) , IEEE Press & Wiley-Interscience, 2002. ISBN 0-471-22782-X.
  • Sheldon X.-D. Tan, Esteban Tlelo-Cuautle, “Recent development in symbolic analysis: an overview”, Chapter in Design of Analog Circuits through Symbolic Analysis, M. Fakhfakh, E. Tlelo-Cuautle and F.V. Fernández (Editors.), Bentham Science Publishers Ltd (www.ebook-engineering.org), ISBN: 9078-1-60805-095-6, 2011 (in press).
  • Sheldon X.-D. Tan, “Symbolic analysis by determinant decision diagrams and applications”, Chapter in Design of Analog Circuits through Symbolic Analysis, M. Fakhfakh, E. Tlelo-Cuautle and F.V. Fernández (Editors.), Bentham Science Publishers Ltd (www.ebook-engineering.org), ISBN: 9078-1-60805-095-6, 2011 (in press).
  • Esteban Tlelo-Cuautle, Carlos Sanchez-Lopez, Elyoenai Martinez-Romero, Sheldon X.-D. Tan, Peng Li, Francisco Fernandez and Mourad Fakhfakh, “Behavioral modeling of mixed-mode integrated circuits”, Esteban Tlelo-Cuautle, Editor, Chapter in “Advances in Analog Circuits", INTECH (www.intechweb.org), ISBN 978-953-307-323-1, Feb., 2011.
  • Xue-Xin Liu, Hao Yu, Hai Wang, Sheldon X.-D. Tan, “Analog mismatch analysis by stochastic nonlinear macromodeling”, Chapter in “Analog Circuits: Applications, Design and Performances”, E. Tlelo-Cuautle (Editor), NOVA Science Publishers Inc. ISBN: 978-1-61324-355-8. Sept., 2011
  • Sheldon X.-D. Tan, Xue-Xin Liu and Eric Mlinar, and Esteban Tlelo-Cuautle, “Parallel symbolic analysis of large analog circuits on GPU platforms”, Chapter in "VLSI Design", Esteban Tlelo-Cuautle and Sheldon X.-D. Tan (Editors), INTECH (www.intechweb.org), ISBN 979-953-307-512-8, 2011 (in press)
  • Sheldon X.-D. Tan, “Symbolic Analysis of Large Analog Circuits with Determinant Decision Diagrams”, University of Iowa, 1999.

 

Journal publications

  • C.-J. Shi and X.-D. Tan. “Canonical symbolic analysis of large analog circuits with determinant decision diagrams.” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 19, no. 1, pp. 1-18, 2000.
  • X.-D. Tan and C.-J. Shi. “Hierarchical symbolic analysis of analog integrated circuits via determinant decision diagrams.” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 19, no. 4, pp. 401-412, 2000.
  • C.-J. Shi and X.-D. Tan. “Compact representation and efficient generation of s-expanded symbolic network functions for computer-aided analog circuit design.” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 20, no. 7, pp. 813-827, 2001.
  • S. X.-D. Tan and C-J. Shi. “Efficient DDD-based interpretable symbolic characterization of large analog circuits”, IEICE Transactions on Fundamentals, pp.3112-3118, vol. E86-A, No.12, Dec. 2003.
  • S. X.-D. Tan and C-J. Shi, “Efficient approximation of symbolic expressions for analog behavioral modeling and analysis.” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 23, No.6, pp. 907-918, June 2004.
  • S. X.-D. Tan, “A general hierarchical circuit modeling and simulation algorithm”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 24, no. 3, pp. 418-434, March 2005.
  • X.-D. S. Tan, W. Guo and Z. Qi, “Hierarchical approach to exact symbolic analysis of large analog circuits”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 24, no. 8, pp. 1241-1250, 2005.
  • S. X-D. Tan, “Symbolic analysis of analog circuits by Boolean logic operations”, IEEE Trans. Circuit and Systems-II, vol. 53, no. 11, pp.1313-1317, Nov. 2006.
  • E. Tlelo-Cuautle, C. Sanchez-Lopez, E. Martınez-Romero, S. X.-D. Tan, “Symbolic analysis of analog circuits containing voltage mirrors and current mirrors”, Analog Integr Circ Sig Process, vol. 65, no. 1, pp. 89-95, 2010, (online permanent DOI Link)
  • C. Sánchez-López, F.V. Fernández, E. Tlelo-Cuautle, S. X.-D. Tan, “Pathological element-based active device models and their application to symbolic analysis,” IEEE Transactions on Circuits and Systems I (TCAS-I) , vol. 58, no 6, pp.1382-1395, 2011.

 

Conference publications

  • C.-J. Shi and X.-D. Tan, “Symbolic analysis of large analog circuits by determinant decision diagrams,” Proc. IEEE International Conference on Computer-Aided Design (ICCAD'97), San Jose, CA. Nov. 1997, pp. 366-373.
  • C.-J. Shi and X.-D. Tan, “Efficient derivation of exact s-expanded symbolic expressions for behavioral modeling of analog circuits,” Proc. IEEE Custom Integrated Circuits Conference (CICC98), Santa Clara, CA, May, 1998, pp. 463-466.
  • X.-D. Tan and C.-J Shi, “Hierarchical symbolic analysis of large analog circuits with determinant decision diagrams,” Proc. IEEE International Symposium on Circuits and Systems (ISCAS), vol. VI, Monterey, CA. May 31-June 3, 1998, pp. 318-321.
  • X.-D. Tan and C.-J. Shi, “Interpretable symbolic small-signal characterization of large analog circuits using determinant decision diagrams,” Proc. Design, Automation and Test in Europe (DATE'99), Munich, Germany, Mar. 10-13, 1999, pp. 448-453
  • X.-D. Tan and C.-J. Shi., “Symbolic circuit-noise analysis and modeling via determinant decision diagrams,” Proc. Asia and South Pacific Design Automation Conference (ASP-DAC'00), Yokohama, Japan. Jan. 2000, pp. 283-287.
  • X.-D. S. Tan, C.-J. Richard Shi, “Parametric analog behavioral modeling based on cancellation-free DDDs”, IEEE International Workshop on Behavioral Modeling and Simulation (BMAS’02), Santa Rosa, CA, Oct., 2002.
  • S. X.-D. Tan, C.-J. Shi, “Efficient DDD-based term generation algorithm for analog circuit behavioral modeling,” Proc. Asia South Pacific Design Automation Conference (ASP-DAC’03), Kitakyushu, Japan, Jan. 2003, pp.789-794.
  • S. X.-D. Tan, “A general s-domain hierarchical network reduction algorithm”, Proc. IEEE/ACM International Conf. on Computer-Aided Design (ICCAD), San Jose, CA, pp. 650-657, Nov. 2003.
  • J. Yang and S. X.-D. Tan, “Behavioral modeling of analog circuits by dynamic semi-symbolic analysis”, Proc. IEEE International Symposium on Circuits and Systems (ISCAS), Vancouver, pp. V105-108, May, 2004.
  • J. Yang and S. X.-D. Tan, “An efficient algorithm for transient and distortion analysis of mildly nonlinear analog circuits”, Proc. IEEE International Symposium on Circuits and Systems (ISCAS), Vancouver, Canada, pp. V129-132, May, 2004.
  • S. X.-D. Tan and W. Guo and Z. Qi, “Hierarchical approach to exact symbolic analysis of large analog circuits”, Proc. 41th IEEE/ACM Design Automation Conference (DAC’2004), pp.860-863, San Diego , CA, 2004.
  • Z. Qi, S. X.-D. Tan, P. Liu, “Efficient analog circuit modeling by Boolean logic operations”, IEEE International Workshop on Behavioral Modeling and Simulation (BMAS), pp. 76-81, San Jose, CA, Sept., 2005.
  • E. Tlelo-Cuautle, E. Martínez-Romero, C. Sánchez-López, S. X.-D. Tan, “Symbolic formulation method for mixed-mode analog circuits using nullors”, In Proc. 16th IEEE International Conference on Electronics, Circuits and Systems (ICECS’09), pp.856-859, Hammamet, Tunisia, Dec. 2009.
  • E. Tlelo-Cuautle, E. Martínez-Romero, C. Sánchez-López, S. X.-D. Tan, “Symbolic behavioral modeling of low voltage amplifiers”, IEEE International Conference on Electrical Engineering, Computing Science and Automatic Control (CCE), México, pp.510-514, September 8-10, 2010.
  • E. Martínez-Romero, E. Tlelo-Cuautle, C. Sánchez-López, S. X.-D. Tan, “Symbolic noise analysis of low voltage amplifiers by using nullors”, IEEE International Workshop on Symbolic and Numerical Methods, Modeling and Applications to Circuit Design (SM2ACD), Tunisia, October 5-6, 2010.
  • J. Lu, Z. Hao, S. X.-D. Tan, “Graph-based parallel analysis of large analog circuits based on GPU platforms”, ACM International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU Workshop), Santa Barbara, April 2011.
  • Z. Hao, S. X.-D. Tan, R. Shen, G. Shi, “Performance bound analysis of analog circuits considering process variations”, Proc. IEEE/ACM Design Automation Conference (DAC’11) , pp.310-315, San Diego, CA, June 2011.
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